The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. When PL is HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on CE will disable the CP input. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications.

The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications.

The HEF4093B is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals.

The 74AHC1G08; 74AHCT1G08 is a single 2-input AND gate. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments.                           • Wide supply voltage range from 2.0 to 5.5 V

• Overvoltage tolerant inputs to 5.5 V

• High noise immunity

• CMOS low power dissipation

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level A

• Symmetrical output impedance

• Balanced propagation delays

• Input levels:

• For 74AHC1G08: CMOS level

• For 74AHCT1G08: TTL level

• ESD protection:

• HBM JESD22-A114E: exceeds 2000 V

• MM JESD22-A115-A: exceeds 200 V

• CDM JESD22-C101C: exceeds 1000 V

• Specified from -40 °C to +125 °C

The TDA8920C is a high-efficiency class-D audio power amplifier. The typical output

power is 2 × 110 W with a speaker load impedance of 4 Ω.

The TDA8920C is available in both HSOP24 and DBS23P power packages. The amplifier

operates over a wide supply voltage range from ±12.5 V to ±32.5 V and features low

quiescent current consumption.             ■ Pin compatible with TDA8950/20B for both HSOP24 and DBS23P packages

■ Symmetrical operating supply voltage range from ±12.5 V to ±32.5 V

■ Stereo full differential inputs, can be used as stereo Single-Ended (SE) or mono

Bridge-Tied Load (BTL) amplifier

■ High output power in typical applications:

◆ SE 2 × 110 W, RL = 4 Ω (VP = ±30 V)

◆ SE 2 × 125 W, RL = 4 Ω (VP = ±32 V)

◆ SE 2 × 120 W, RL = 3 Ω (VP = ±29 V)

◆ BTL 1 × 220 W, RL = 8 Ω (VP = ±30 V)

■ Low noise

■ Smooth pop noise-free start-up and switch off

■ Zero dead time switching

■ Fixed frequency

■ Internal or external clock

■ High efficiency

■ Low quiescent current

■ Advanced protection strategy: voltage protection and output current limiting

■ Thermal FoldBack (TFB)

■ Fixed gain of 30 dB in SE and 36 dB in BTL applications

■ Fully short-circuit proof across load

■ BD modulation in BTL configuration

45 V, 100 mA NPN general-purpose transistors

NPN general-purpose transistors in a very small SOT323 (SC-70) Surface-Mounted Device (SMD) plastic package.

PNP general-purpose transistor in a small SOT23 (TO-236AB) Surface-Mounted Device (SMD) plastic package.

NPN complement: PMBS3904                   

• 100 mA collector current capability       Applications：

• General-purpose switching and amplification                       

The MPL3115A2 is a compact, piezoresistive, absolute pressure sensor with an I2C digital interface. MPL3115A2 has a wide operating range of 20 kPa to 110 kPa, a range that covers all surface elevations on earth. The MEMS is temperature compensated utilizing an on-chip temperature sensor. The pressure and temperature data is fed into a high resolution ADC to provide fully compensated and digitized outputs for pressure in Pascals and temperature in °C. The compensated pressure output can then be converted to altitude, utilizing the formula stated in Section 8.1.3 "Pressure/altitude" provided in meters.The internal processing in MPL3115A2 removes compensation and unit conversion load from the system MCU, simplifying system design.

MPL3115A2's advanced ASIC has multiple user programmable modes such as power saving, interrupt and autonomous data acquisition modes, including programmed acquisition cycle timing, and poll-only modes. Typical active supply current is 40 μA per measurement-second for a stable 10 cm output resolution.

The MPX5500 series piezoresistive transducer is a state-of-the-art monolithic silicon pressure sensor designed for a wide range of applications, but particularly those employing a microcontroller or microprocessor with A/D inputs. This patented, single element transducer combines advanced micromachining techniques, thin-film metallization, and bipolar processing to provide an accurate, high level analog output signal that is proportional to the applied pressure.

The MMA8451Q is a smart, low-power, three-axis, capacitive, micromachined accelerometer with 14 bits of resolution. This accelerometer is packed with embedded functions with flexible user programmable options, configurable to two interrupt pins. Embedded interrupt functions allow for overall power savings relieving the host processor from continuously polling data. There is access to both low-pass filtered data as well as high-pass filtered data, which minimizes the data analysis required for jolt detection and faster transitions. The device can be configured to generate inertial wakeup interrupt signals from any combination of the configurable embedded functions allowing the MMA8451Q to monitor events and remain in a low-power mode during periods of inactivity. The MMA8451Q is available in a 16-pin QFN, 3 mm x 3 mm x 1 mm package. 

The MMA8452Q is a smart, low-power, three-axis, capacitive, micromachined accelerometer with 12 bits of resolution. This accelerometer is packed with embedded functions with flexible user programmable ptions, configurable to two interrupt pins. Embedded interrupt functions allow for overall power savings relieving the host processor from continuously polling data. 

The MMA8452Q has user selectable full scales of ±2 g/±4 g/±8 g with high-pass filtered data as well as non-filtered data available real-time. The device can be configured to generate inertial wakeup interrupt signals from any combination of the configurable embedded functions allowing the MMA8452Q to monitor events and remain in a low-power mode during periods of inactivity. The MMA8452Q is available in a 16-pin QFN, 3 mm x 3 mm x 1 mm package. 

The temperature sensors in the KTY81 series have a positive temperature coefficient of resistance and are suitable for use in measurement and control systems. The sensors are encapsulated in the SOD70 2 in-line leads plastic package. Other special selections are available on request

Quadruple ESD transient voltage suppressor

Monolithic transient voltage suppressor diode in a six lead SOT457 (SC-74) package for 4-bit wide ESD transient suppression at 5.6 V level.

Low capacitance bidirectional ElectroStatic Discharge (ESD) protection diode in a very small SOD323 (SC-76) Surface-Mounted Device (SMD) plastic package designed to protect one signal line from the damage caused by ESD and other transients.                           

• Bidirectional ESD protection of one line

• Low diode capacitance: Cd = 2.9 pF

• Ultra low leakage current: IRM = 5 nA

• ESD protection of up to 10 kV

• IEC 61000-4-2, level 4 (ESD)

• AEC-Q101 qualified                       

Applications：

• Computers and peripherals

• Audio and video equipment

• Cellular handsets and accessories

• 10/100/1000 Ethernet

• Local Area Network (LAN) equipment

• Communication systems

• Portable electronics

• SIM card protection

• High-speed data lines    

Uni-directional double ESD protection diodes in a SOT23 plastic package. Designed to protect up to two transmission or data lines from ElectroStatic Discharge (ESD) damage.  • Uni-directional ESD protection of up to two lines

• Max. peak pulse power: Ppp = 330 W at tp = 8/20 µs

• Low clamping voltage: V(CL)R = 20 V at Ipp = 18 A

• Ultra-low reverse leakage current: IRM < 700 nA

• ESD protection > 23 kV

• IEC 61000-4-2; level 4 (ESD)

• IEC 61000-4-5 (surge); Ipp = 18 A at tp = 8/20 µs                               

APPLICATIONS：

• Computers and peripherals

• Communication systems

• Audio and video equipment

• High speed data lines

• Parallel ports.

The P82B715 is a bipolar IC intended for application in I2C-bus and derivative bus systems. While retaining all the operating modes and features of the I2C-bus it permits extension of the practical separation distance between components on the I2C-bus by buffering both the data (SDA) and the clock (SCL) lines. The I2C-bus capacitance limit of 400 pF restricts practical communication distances to a few meters. Using one P82B715 at each end of a long cable (connecting Lx/Ly to Lx/Ly) reduces that cable’s loading on the linked I2C-buses by a factor of 10 and allows the total system capacitance load (all devices, cable, connectors, and traces or wires connected to the I2C-bus) to be around 3000 pF while the loading on each I2C-bus on the Sx/Sy sides remains below 400 pF. Longer cables or low-cost, general-purpose wiring may be used to link I2C-bus based modules without degrading noise margins. Multiple P82B715s can be connected together, linking their Lx/Ly ports, in a star or multi-point architecture as long as the total capacitance of the system is less than about 3000 pF and each bus at an Sx/Sy connection is well below 400 pF. This configuration, with the master and/or slave devices attached to the Sx/Sy port of each P82B715, has full multi-master communication capability. The P82B715 alone does not support voltage level translation, but it can be simply implemented using low cost transistors when required. There is no restriction on interconnecting the Sx/Sy I/Os, and, because the device output levels are always held within 100 mV of input drive levels, P82B715 is compatible with bus buffers that use voltage level offsets, e.g., PCA9511A, PCA9517, Sx/Sy side of P82B96

The PCA9515 is a BiCMOS integrated circuit intended for application in I2C-bus and SMBus systems. While retaining all the operating modes and features of the I2C-bus system, it permits extension of the I2C-bus by buffering both the data (SDAn) and the clock (SCLn) lines, thus enabling two buses of 400 pF. The I2C-bus capacitance limit of 400 pF restricts the number of devices and bus length.Using the PCA9515 enables the system designer to isolate two halves of a bus, thus moredevices or longer length can be accommodated. It can also be used to run two buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz bus is isolated when 400 kHz operation of the other is required

The PCA9306 is a dual bidirectional I2C-bus and SMBus voltage-level translator with an enable (EN) input, and is operational from 1.0 V to 3.6 V (Vref(1)) and 1.8 V to 5.5 V (Vbias(ref)(2)).

The PCA9306 allows bidirectional voltage translations between 1.0 V and 5 V without the use of a direction pin. The low ON-state resistance (Ron) of the switch allows connections to be made with minimal propagation delay. When EN is HIGH, the translator switch is on, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively, allowing bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high-impedance state exists between ports.

The PCA9306 is not a bus buffer like the PCA9509 or PCA9517A that provide both level translation and physically isolate the capacitance to either side of the bus when both sides are connected. The PCA9306 only isolates both sides when the device is disabled and provides voltage level translation when active.

The PCA9511A is a hot swappable I2C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command orbus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9511A provides bidirectional buffering, keeping the backplane and card capacitances isolated.

The PCA9511A rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements. The PCA9511A incorporates a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a low current mode when asserted LOW, and an open-drain READY output pin, which indicates that the backplane and card sides are connected together (HIGH) or not (LOW). During insertion, the PCA9511A SDA and SCL lines are precharged to 1 V to minimize the current required to charge the parasitic capacitance of the chip

The PCA9515A is a CMOS integrated circuit intended for application in I2C-bus and SMBus systems. While retaining all the operating modes and features of the I2C-bus system, it permits  extension of the I2C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF.

The I2C-bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9515A enables the system designer to isolate two halves of a bus, thus more devices or longer length can be accommodated. It can also be used to run two buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz bus is isolated when 400 kHz operation of the other is required

The PCA9517A is a CMOS integrated circuit that provides level shifting between low  voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications. While retaining all the operating modes and features of the I2C-bus system during the level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Using the PCA9517A enables the system designer to isolate two halves of a bus for both voltage and capacitance. The SDA and SCL pins are overvoltage tolerant and are high-impedance when the PCA9517A is unpowered

The SJA1000 is a stand-alone controller for the Controller Area Network (CAN) used within automotive and general industrial environments. It is the successor of the PCA82C200 CAN controller (BasicCAN) from Philips Semiconductors. Additionally, a new mode of operation is implemented (PeliCAN) which supports the CAN 2.0B protocol specification with several new features

The TJA1021 is the interface between the Local Interconnect Network (LIN) master/slave protocol controller and the physical bus in a LIN. It is primarily intended for in-vehicle sub-networks using baud rates from 1 kBd up to 20 kBd (/20 variant) and is compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A, SAE J2602 and ISO 17987-4:2016 (12 V). The TJA1021 is pin-to-pin compatible with the TJA1020 and MC33662(B).

The transmit data stream of the protocol controller at the transmit data input (TXD) is converted by the TJA1021 into a bus signal with optimized slew rate and wave shaping to minimize ElectroMagnetic Emission (EME). The LIN bus output pin is pulled HIGH via an internal termination resistor. For a master application, an external resistor in series with a diode should be connected between pin INH or pin VBAT and pin LIN. The receiver detects the data stream at the LIN bus input pin and transfers it via pin RXD to the microcontroller.

In Sleep mode, the power consumption of the TJA1021 is very low. In failure modes, the power consumption is reduced to a minimum

The PCA9508 is a CMOS integrated circuit that supports hot-swap with zero offset and provides level shifting between low voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) for I2C-bus or SMBus applications. While retaining all the operating modes and features of the I2C-bus system during the level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Using the PCA9508 enables the system designer to isolate two halves of a bus for both voltage and capacitance, and perform hot-swap and voltage level translation. Furthermore, the dual supply pins can be powered up in any sequence; when any of the supply pins are unpowered, the 5 V tolerant I/O are high-impedance.

The TJA1041A provides an advanced interface between the protocol controller and the physical bus in a Controller Area Network (CAN) node. The TJA1041A is primarily intended for automotive high-speed CAN applications (up to 1 Mbit/s). The transceiver provides differential transmit capability to the bus and differential receive capability to the CAN controller. The TJA1041A is fully compatible to the ISO 11898 standard, and offers excellent ElectroMagnetic Compatibility (EMC) performance, very low power consumption, and passive behavior when supply voltage is off. The advanced features include:

• Low-power management, supporting local and remote wake-up with wake-up source recognition and the capability to control the power supply in the rest of the node

• Several protection and diagnosis functions including short circuits of the bus lines and first battery connection

• Automatic adaptation of the I/O-levels, in line with the supply voltage of the controlle

The PCA82C251 is the interface between a CAN protocol controller and the physical bus. 

The device provides differential transmit capability to the bus and differential receive capability to the CAN controller

The TJA1145A is a high-speed CAN transceiver that provides an interface between a 

Controller Area Network (CAN) protocol controller and the physical two-wire CAN bus. The transceiver is designed for high-speed CAN applications in the automotive industry, providing differential transmit and receive capability to (a microcontroller with) a CAN protocol controller.

The TJA1145A features very low power consumption in Standby and Sleep modes and 

supports ISO 11898-2:2016 compliant CAN Partial Networking by means of a selective 

wake-up function                             

 ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5 compliant

 Timing guaranteed for data rates up to 5 Mbit/s in the CAN FD fast phase

 Autonomous bus biasing

 Optimized for in-vehicle high-speed CAN communication

 No ‘false’ wake-ups due to CAN FD in TJA1145Ax/FD variant

P-channel enhancement mode Field-Effect Transistor (FET) in a small SOT23 (TO-236AB) Surface-Mounted Device (SMD) plastic package using Trench MOSFET technology.

N-channel enhancement mode Field-Effect Transistor (FET) in a small SOT23 (TO-236AB) Surface-Mounted Device (SMD) plastic package using Trench MOSFET technology.